The present invention relates to methods of joining a microelectronic chip to a laminate, and particularly to methods of using magnets to maintain laminate flatness while joining the microelectronic chip to the laminate.
FIG. 1A depicts an exemplary process of joining a microelectronic chip 20 to a laminate 10 by, for example, a plurality of solder balls 30. To improve the electrical connection between the microelectronic chip 20 and the laminate 10 through the solder balls 30 a reflow process may be used, as depicted in FIG. 1B. During the reflow process, thermal stress may cause warpage of the laminate 10. Laminate warpage or warping may be defined by the laminate's curvature from a flat surface of the bottom of the laminate. Alternatively, laminate warpage may be measured relative to a planar surface mating with the bottom of the laminate.
Particularly as organic laminates grow thinner, the degree of laminate warpage may grow to undesirable levels. Among negative effects, laminate warpage may lead to opens where the laminate is no longer joined to all of the solder balls, as depicted in FIG. 1B, or shorts where adjacent solder balls come into contact. Warpage may further result in cracking of the laminate or separation of the dielectric layers within the laminate. Increased laminate warpage during die reflow can also lead to increased module warpage at the end of a bond and assembly process, which can cause the module to fail final co-planarity specifications
It would therefore be desirable to provide an apparatus and method for maintaining laminate flatness throughout the chip joining process, particularly during solder reflow.